Search - uart verilog

[VHDL-FPGA-Verilog] uart_hw_test

Description: uart hardware test in verilog
Platform: | Size: 4308992 | Author: Ni Ni | Hits:

[VHDL-FPGA-Verilog] uart

Description: UART的串口程序，收发功能都已实现，直接可用(UART serial procedures, transceiver functions have been achieved, directly available)
Platform: | Size: 2048 | Author: 上腾娱乐 | Hits:

[VHDL-FPGA-Verilog] verilog uart v1.0

Description: 基于Verilog语言写的UART模块，非常实用，可以参考，希望共同进步(Based on the Verilog language to write the UART module, very practical, you can refer to, hope to make progress together)
Platform: | Size: 2847744 | Author: 骑士1234 | Hits:

[VHDL-FPGA-Verilog] uart

Description: 实现与电脑端串行数据发送与接收，波特率为9600(Realize serial data sending and receiving with the computer terminal)
Platform: | Size: 1024 | Author: hurricanhup | Hits:

[Other] UART_source_code

Description: uart verilog code for nexys2 fpga borad
Platform: | Size: 3072 | Author: posljh | Hits:

[VHDL-FPGA-Verilog] xuartps_intr_example

Description: microblaze uart vivado(vivado microblaze interrupt)
Platform: | Size: 4096 | Author: xilinxer | Hits:

[VHDL-FPGA-Verilog] uart

Description: 用Verilog实现FPGA的uart的串行通信功能，并附有testbench(The serial communication function of FPGA of UART is realized with Verilog, and Testbench is attached)
Platform: | Size: 308224 | Author: 怪了个乖 | Hits:

[e-language] uart-master

Description: verilog语言实现URAT串口通信，便捷开发(Implementation of various basic circuits in digital circuits with Verilog language)
Platform: | Size: 3072 | Author: Maren | Hits:

[Com Port] uart

Description: 一个具有固定波特率的 UART 串口收发器，可以实现串口收发器，可以实现 9600 波特率的串口通信，能够与 PC 机串口进行通信，支持 8 比特数据位、 1 比特停止位、无校验硬件流控模式(A fixed baud rate UART serial transceiver, can realize serial transceiver, can achieve 9600 baud rate serial communication, and can communicate with PC serial port, support 8 bit data bit, 1 bit stop bit, no verification hardware flow control mode)
Platform: | Size: 452608 | Author: 寒山 | Hits:

[VHDL-FPGA-Verilog] eetop.cn_uart 源码 (Verilog)

Description: Verilog编写的UART通信模块，比较清晰(UART model wrote by Verilog)
Platform: | Size: 9216 | Author: jackey527 | Hits:

[VHDL-FPGA-Verilog] test_uart

Description: 该资料包含用FPGA（EP4CE22F17型号）编写的UART通信程序，最重要的是里面含有串口波特率可调，包括一些常见的波特率。(This information includes UART communication program written by FPGA (EP4CE22F17 model), and most importantly, it contains serial port baud rate tunable, including some common baud rate.)
Platform: | Size: 3358720 | Author: 杨雷 | Hits:

[VHDL-FPGA-Verilog] uart

Description: FPGA Verilog设计UART通讯程序(UART communication code with Verilog in FPGA)
Platform: | Size: 117760 | Author: gq_zhou | Hits:

[VHDL-FPGA-Verilog] UART

Description: 本人用verilog编写的UART协议，经测试可用。(I am prepared to use verilog UART protocol, the test is available.)
Platform: | Size: 517120 | Author: chenpeiweiweiwei | Hits:

[VHDL-FPGA-Verilog] Receiver_spartn6_v1

Description: Implement design of UART receiver in verilog
Platform: | Size: 40960 | Author: Armaghan | Hits:

[VHDL-FPGA-Verilog] uart

Description: UART接口的基于FPGA芯片，用Verilog语言实现，在quartus上操作(UART interface is implemented by FPGA)
Platform: | Size: 3961856 | Author: 恰同学少年111 | Hits:

[Other] verilog

Description: lcd1602 12864显示程序代码，串口传输数据代码(lcd1602 12864 code,UART code.)
Platform: | Size: 7168 | Author: 打蛋器 | Hits:

[Internet-Network] apb-uart

Description: apb—uart模块，实现中断处理和异步收发数据并处理(APB - UART module, interrupting processing and asynchronous receiving and receiving data and processing)
Platform: | Size: 4096 | Author: 王大柱 | Hits:

[VHDL-FPGA-Verilog] uart

Description: 此上传文件实现的功能就是FPGA里实现从PC接收数据，然后把接收到的数据发回去。使用的是串口UART协议进行收发数据。(The function of this upload file is to receive data from PC in FPGA and send back the received data.The serial port UART protocol is used to receive and receive data.)
Platform: | Size: 1649664 | Author: 木子桶 | Hits:

[Documents] 黑金Sparten6开发板Verilog教程V1.6

Description: 黑金spartan的开发板教程，包含了各类接口如spi，uart，vga的用例，以及各项存储器如flash，ddr的操作方法(spartan 6 example design)
Platform: | Size: 19894272 | Author: 爱的分啥 | Hits:

[VHDL-FPGA-Verilog] apb_uart

Description: 这里是apb总线设计代码。这个源程序是基于verilog语言设计的(Here is the APB bus design code. This source program is designed based on Verilog language)
Platform: | Size: 2048 | Author: megmand | Hits:

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[VHDL-FPGA-Verilog] uart_hw_test

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] verilog uart v1.0

[VHDL-FPGA-Verilog] uart

[Other] UART_source_code

[VHDL-FPGA-Verilog] xuartps_intr_example

[VHDL-FPGA-Verilog] uart

[e-language] uart-master

[Com Port] uart

[VHDL-FPGA-Verilog] eetop.cn_uart 源码 (Verilog)

[VHDL-FPGA-Verilog] test_uart

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] Receiver_spartn6_v1

[VHDL-FPGA-Verilog] uart

[Other] verilog

[Internet-Network] apb-uart

[VHDL-FPGA-Verilog] uart

[Documents] 黑金Sparten6开发板Verilog教程V1.6

[VHDL-FPGA-Verilog] apb_uart

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